Statement of the Invention
This invention relates to a ramp release and reset circuit and, more particularly, to a logical ramp release and reset circuit for a three phase, SCR phase controlled, voltage regulator which is relatively free of timing variations due to motor/generator wave distortion.
Ramp release and reset circuits have introduced timing variations in the ramp generated because of distortion in the input waves. For example, the three phase silicon controlled rectifier (SCR) voltage controlled regulators used extensively in the computer industry have been found to contain voltage variations due to the distortion in the sinusoidal wave inputs from motor generator sets when large load changes occur. The motor generator sets have been found to produce distortion in their output which is somewhat proportional to current load. This distortion in turn, as mentioned above, causes the ramp release and reset circuit output to vary in time, thereby generating a ramp having an unstable release and start time. The firing angle is determined by the time the ramp crosses the error voltage. A pulse is produced at the intersection of the two voltages which is used to trigger the gate of the silicon controlled rectifier (SCR), thereby turning it on. The prior art ramp release and reset circuits consist of what are popularly known as zero crossover circuits which produce a short pulse at the zero crossover point on the input sinewave. The ramp is released at the end of a pulse and is reset at the beginning of the next pulse. Thus, the ramp when compared to a particular voltage level should give a consistent firing angle output. However, this output is not consistent since the ramps tend to have different starting times because of the varying width of the zero crossover pulses and, accordingly, cross the error voltage at different points. The zero crossover pulses, as previously mentioned, vary in width because of the distortion in the sinewave which is utilized to generate the zero crossover pulse.